22 #include <va/va_enc_hevc.h>
96 char *
data,
size_t *data_len,
110 "%zu < %zu.\n", *data_len,
132 "type = %d.\n",
header->nal_unit_type);
140 char *
data,
size_t *data_len)
174 char *
data,
size_t *data_len)
200 char *
data,
size_t *data_len)
238 *
type = VAEncPackedHeaderRawData;
258 VAEncSequenceParameterBufferHEVC *vseq =
ctx->codec_sequence_params;
259 VAEncPictureParameterBufferHEVC *vpic =
ctx->codec_picture_params;
264 memset(
vps, 0,
sizeof(*
vps));
265 memset(
sps, 0,
sizeof(*
sps));
266 memset(
pps, 0,
sizeof(*
pps));
271 if (
desc->nb_components == 1) {
274 if (
desc->log2_chroma_w == 1 &&
desc->log2_chroma_h == 1) {
276 }
else if (
desc->log2_chroma_w == 1 &&
desc->log2_chroma_h == 0) {
278 }
else if (
desc->log2_chroma_w == 0 &&
desc->log2_chroma_h == 0) {
282 "%s is not supported.\n",
desc->name);
294 .nuh_temporal_id_plus1 = 1,
297 vps->vps_video_parameter_set_id = 0;
299 vps->vps_base_layer_internal_flag = 1;
300 vps->vps_base_layer_available_flag = 1;
301 vps->vps_max_layers_minus1 = 0;
302 vps->vps_max_sub_layers_minus1 = 0;
303 vps->vps_temporal_id_nesting_flag = 1;
343 ctx->surface_width,
ctx->surface_height,
344 ctx->nb_slices,
ctx->tile_rows,
ctx->tile_cols,
345 (
ctx->b_per_p > 0) + 1);
351 "any normal level; using level 8.5.\n");
358 vps->vps_sub_layer_ordering_info_present_flag = 0;
359 vps->vps_max_dec_pic_buffering_minus1[0] =
ctx->max_b_depth + 1;
360 vps->vps_max_num_reorder_pics[0] =
ctx->max_b_depth;
361 vps->vps_max_latency_increase_plus1[0] = 0;
363 vps->vps_max_layer_id = 0;
364 vps->vps_num_layer_sets_minus1 = 0;
365 vps->layer_id_included_flag[0][0] = 1;
367 vps->vps_timing_info_present_flag = 1;
371 vps->vps_poc_proportional_to_timing_flag = 1;
372 vps->vps_num_ticks_poc_diff_one_minus1 = 0;
376 vps->vps_poc_proportional_to_timing_flag = 0;
378 vps->vps_num_hrd_parameters = 0;
386 .nuh_temporal_id_plus1 = 1,
389 sps->sps_video_parameter_set_id =
vps->vps_video_parameter_set_id;
391 sps->sps_max_sub_layers_minus1 =
vps->vps_max_sub_layers_minus1;
392 sps->sps_temporal_id_nesting_flag =
vps->vps_temporal_id_nesting_flag;
394 sps->profile_tier_level =
vps->profile_tier_level;
396 sps->sps_seq_parameter_set_id = 0;
398 sps->chroma_format_idc = chroma_format;
399 sps->separate_colour_plane_flag = 0;
401 sps->pic_width_in_luma_samples =
ctx->surface_width;
402 sps->pic_height_in_luma_samples =
ctx->surface_height;
404 if (avctx->
width !=
ctx->surface_width ||
406 sps->conformance_window_flag = 1;
407 sps->conf_win_left_offset = 0;
408 sps->conf_win_right_offset =
409 (
ctx->surface_width - avctx->
width) >>
desc->log2_chroma_w;
410 sps->conf_win_top_offset = 0;
411 sps->conf_win_bottom_offset =
412 (
ctx->surface_height - avctx->
height) >>
desc->log2_chroma_h;
414 sps->conformance_window_flag = 0;
420 sps->log2_max_pic_order_cnt_lsb_minus4 = 8;
422 sps->sps_sub_layer_ordering_info_present_flag =
423 vps->vps_sub_layer_ordering_info_present_flag;
424 for (
i = 0;
i <=
sps->sps_max_sub_layers_minus1;
i++) {
425 sps->sps_max_dec_pic_buffering_minus1[
i] =
426 vps->vps_max_dec_pic_buffering_minus1[
i];
427 sps->sps_max_num_reorder_pics[
i] =
428 vps->vps_max_num_reorder_pics[
i];
429 sps->sps_max_latency_increase_plus1[
i] =
430 vps->vps_max_latency_increase_plus1[
i];
437 sps->log2_min_luma_coding_block_size_minus3 = 0;
438 sps->log2_diff_max_min_luma_coding_block_size = 2;
440 sps->log2_min_luma_transform_block_size_minus2 = 0;
441 sps->log2_diff_max_min_luma_transform_block_size = 3;
443 sps->max_transform_hierarchy_depth_inter = 3;
444 sps->max_transform_hierarchy_depth_intra = 3;
446 sps->amp_enabled_flag = 1;
448 sps->sample_adaptive_offset_enabled_flag = 0;
449 sps->sps_temporal_mvp_enabled_flag = 0;
451 sps->pcm_enabled_flag = 0;
454 #if VA_CHECK_VERSION(1, 13, 0)
456 VAConfigAttribValEncHEVCFeatures features = { .value = priv->
va_features };
459 sps->amp_enabled_flag =
461 sps->sample_adaptive_offset_enabled_flag =
463 sps->sps_temporal_mvp_enabled_flag =
464 !!features.bits.temporal_mvp;
465 sps->pcm_enabled_flag =
470 VAConfigAttribValEncHEVCBlockSizes bs = { .value = priv->
va_bs };
471 sps->log2_min_luma_coding_block_size_minus3 =
473 sps->log2_diff_max_min_luma_coding_block_size =
476 sps->log2_min_luma_transform_block_size_minus2 =
477 bs.bits.log2_min_luma_transform_block_size_minus2;
478 sps->log2_diff_max_min_luma_transform_block_size =
479 bs.bits.log2_max_luma_transform_block_size_minus2 -
480 bs.bits.log2_min_luma_transform_block_size_minus2;
482 sps->max_transform_hierarchy_depth_inter =
483 bs.bits.max_max_transform_hierarchy_depth_inter;
484 sps->max_transform_hierarchy_depth_intra =
485 bs.bits.max_max_transform_hierarchy_depth_intra;
492 sps->num_short_term_ref_pic_sets = 0;
493 sps->long_term_ref_pics_present_flag = 0;
495 sps->vui_parameters_present_flag = 1;
501 { 1, 1 }, { 12, 11 }, { 10, 11 }, { 16, 11 },
502 { 40, 33 }, { 24, 11 }, { 20, 11 }, { 32, 11 },
503 { 80, 33 }, { 18, 11 }, { 15, 11 }, { 64, 33 },
504 { 160, 99 }, { 4, 3 }, { 3, 2 }, { 2, 1 },
510 if (num == sar_idc[
i].num &&
511 den == sar_idc[
i].den) {
567 .nuh_temporal_id_plus1 = 1,
570 pps->pps_pic_parameter_set_id = 0;
571 pps->pps_seq_parameter_set_id =
sps->sps_seq_parameter_set_id;
573 pps->num_ref_idx_l0_default_active_minus1 = 0;
574 pps->num_ref_idx_l1_default_active_minus1 = 0;
578 pps->cu_qp_delta_enabled_flag = (
ctx->va_rc_mode != VA_RC_CQP);
579 pps->diff_cu_qp_delta_depth = 0;
582 #if VA_CHECK_VERSION(1, 13, 0)
584 VAConfigAttribValEncHEVCFeatures features = { .value = priv->
va_features };
585 if (
ctx->va_rc_mode != VA_RC_CQP)
586 pps->cu_qp_delta_enabled_flag =
587 !!features.bits.cu_qp_delta;
589 pps->transform_skip_enabled_flag =
590 !!features.bits.transform_skip;
593 if (
pps->cu_qp_delta_enabled_flag)
594 pps->diff_cu_qp_delta_depth =
sps->log2_diff_max_min_luma_coding_block_size;
598 if (
ctx->tile_rows &&
ctx->tile_cols) {
601 pps->tiles_enabled_flag = 1;
602 pps->num_tile_columns_minus1 =
ctx->tile_cols - 1;
603 pps->num_tile_rows_minus1 =
ctx->tile_rows - 1;
608 for (
i = 0;
i <=
pps->num_tile_columns_minus1 &&
609 uniform_spacing;
i++) {
610 if (
ctx->col_width[
i] !=
611 (
i + 1) *
ctx->slice_block_cols /
ctx->tile_cols -
612 i *
ctx->slice_block_cols /
ctx->tile_cols)
615 for (
i = 0;
i <=
pps->num_tile_rows_minus1 &&
616 uniform_spacing;
i++) {
617 if (
ctx->row_height[
i] !=
618 (
i + 1) *
ctx->slice_block_rows /
ctx->tile_rows -
619 i *
ctx->slice_block_rows /
ctx->tile_rows)
622 pps->uniform_spacing_flag = uniform_spacing;
624 for (
i = 0;
i <=
pps->num_tile_columns_minus1;
i++)
625 pps->column_width_minus1[
i] =
ctx->col_width[
i] - 1;
626 for (
i = 0;
i <=
pps->num_tile_rows_minus1;
i++)
627 pps->row_height_minus1[
i] =
ctx->row_height[
i] - 1;
629 pps->loop_filter_across_tiles_enabled_flag = 1;
632 pps->pps_loop_filter_across_slices_enabled_flag = 1;
636 *vseq = (VAEncSequenceParameterBufferHEVC) {
637 .general_profile_idc =
vps->profile_tier_level.general_profile_idc,
638 .general_level_idc =
vps->profile_tier_level.general_level_idc,
639 .general_tier_flag =
vps->profile_tier_level.general_tier_flag,
641 .intra_period =
ctx->gop_size,
642 .intra_idr_period =
ctx->gop_size,
643 .ip_period =
ctx->b_per_p + 1,
644 .bits_per_second =
ctx->va_bit_rate,
646 .pic_width_in_luma_samples =
sps->pic_width_in_luma_samples,
647 .pic_height_in_luma_samples =
sps->pic_height_in_luma_samples,
650 .chroma_format_idc =
sps->chroma_format_idc,
651 .separate_colour_plane_flag =
sps->separate_colour_plane_flag,
652 .bit_depth_luma_minus8 =
sps->bit_depth_luma_minus8,
653 .bit_depth_chroma_minus8 =
sps->bit_depth_chroma_minus8,
654 .scaling_list_enabled_flag =
sps->scaling_list_enabled_flag,
655 .strong_intra_smoothing_enabled_flag =
656 sps->strong_intra_smoothing_enabled_flag,
657 .amp_enabled_flag =
sps->amp_enabled_flag,
658 .sample_adaptive_offset_enabled_flag =
659 sps->sample_adaptive_offset_enabled_flag,
660 .pcm_enabled_flag =
sps->pcm_enabled_flag,
661 .pcm_loop_filter_disabled_flag =
sps->pcm_loop_filter_disabled_flag,
662 .sps_temporal_mvp_enabled_flag =
sps->sps_temporal_mvp_enabled_flag,
665 .log2_min_luma_coding_block_size_minus3 =
666 sps->log2_min_luma_coding_block_size_minus3,
667 .log2_diff_max_min_luma_coding_block_size =
668 sps->log2_diff_max_min_luma_coding_block_size,
669 .log2_min_transform_block_size_minus2 =
670 sps->log2_min_luma_transform_block_size_minus2,
671 .log2_diff_max_min_transform_block_size =
672 sps->log2_diff_max_min_luma_transform_block_size,
673 .max_transform_hierarchy_depth_inter =
674 sps->max_transform_hierarchy_depth_inter,
675 .max_transform_hierarchy_depth_intra =
676 sps->max_transform_hierarchy_depth_intra,
678 .pcm_sample_bit_depth_luma_minus1 =
679 sps->pcm_sample_bit_depth_luma_minus1,
680 .pcm_sample_bit_depth_chroma_minus1 =
681 sps->pcm_sample_bit_depth_chroma_minus1,
682 .log2_min_pcm_luma_coding_block_size_minus3 =
683 sps->log2_min_pcm_luma_coding_block_size_minus3,
684 .log2_max_pcm_luma_coding_block_size_minus3 =
685 sps->log2_min_pcm_luma_coding_block_size_minus3 +
686 sps->log2_diff_max_min_pcm_luma_coding_block_size,
688 .vui_parameters_present_flag = 0,
691 *vpic = (VAEncPictureParameterBufferHEVC) {
692 .decoded_curr_pic = {
693 .picture_id = VA_INVALID_ID,
694 .flags = VA_PICTURE_HEVC_INVALID,
697 .coded_buf = VA_INVALID_ID,
699 .collocated_ref_pic_index =
sps->sps_temporal_mvp_enabled_flag ?
703 .pic_init_qp =
pps->init_qp_minus26 + 26,
704 .diff_cu_qp_delta_depth =
pps->diff_cu_qp_delta_depth,
705 .pps_cb_qp_offset =
pps->pps_cb_qp_offset,
706 .pps_cr_qp_offset =
pps->pps_cr_qp_offset,
708 .num_tile_columns_minus1 =
pps->num_tile_columns_minus1,
709 .num_tile_rows_minus1 =
pps->num_tile_rows_minus1,
711 .log2_parallel_merge_level_minus2 =
pps->log2_parallel_merge_level_minus2,
712 .ctu_max_bitsize_allowed = 0,
714 .num_ref_idx_l0_default_active_minus1 =
715 pps->num_ref_idx_l0_default_active_minus1,
716 .num_ref_idx_l1_default_active_minus1 =
717 pps->num_ref_idx_l1_default_active_minus1,
719 .slice_pic_parameter_set_id =
pps->pps_pic_parameter_set_id,
722 .sign_data_hiding_enabled_flag =
pps->sign_data_hiding_enabled_flag,
723 .constrained_intra_pred_flag =
pps->constrained_intra_pred_flag,
724 .transform_skip_enabled_flag =
pps->transform_skip_enabled_flag,
725 .cu_qp_delta_enabled_flag =
pps->cu_qp_delta_enabled_flag,
726 .weighted_pred_flag =
pps->weighted_pred_flag,
727 .weighted_bipred_flag =
pps->weighted_bipred_flag,
728 .transquant_bypass_enabled_flag =
pps->transquant_bypass_enabled_flag,
729 .tiles_enabled_flag =
pps->tiles_enabled_flag,
730 .entropy_coding_sync_enabled_flag =
pps->entropy_coding_sync_enabled_flag,
731 .loop_filter_across_tiles_enabled_flag =
732 pps->loop_filter_across_tiles_enabled_flag,
733 .pps_loop_filter_across_slices_enabled_flag =
734 pps->pps_loop_filter_across_slices_enabled_flag,
735 .scaling_list_data_present_flag = (
sps->sps_scaling_list_data_present_flag |
736 pps->pps_scaling_list_data_present_flag),
737 .screen_content_flag = 0,
738 .enable_gpu_weighted_prediction = 0,
739 .no_output_of_prior_pics_flag = 0,
743 if (
pps->tiles_enabled_flag) {
744 for (
i = 0;
i <= vpic->num_tile_rows_minus1;
i++)
745 vpic->row_height_minus1[
i] =
pps->row_height_minus1[
i];
746 for (
i = 0;
i <= vpic->num_tile_columns_minus1;
i++)
747 vpic->column_width_minus1[
i] =
pps->column_width_minus1[
i];
788 for (irap_ref = pic; irap_ref; irap_ref = irap_ref->
refs[1]) {
811 .nuh_temporal_id_plus1 = 1,
838 const int mapping[3] = {1, 2, 0};
839 const int chroma_den = 50000;
840 const int luma_den = 10000;
842 for (
i = 0;
i < 3;
i++) {
843 const int j = mapping[
i];
885 clli->max_pic_average_light_level =
FFMIN(clm->
MaxFALL, 65535);
891 vpic->decoded_curr_pic = (VAPictureHEVC) {
902 href =
ref->priv_data;
904 vpic->reference_frames[
i] = (VAPictureHEVC) {
905 .picture_id =
ref->recon_surface,
908 VA_PICTURE_HEVC_RPS_ST_CURR_BEFORE : 0) |
910 VA_PICTURE_HEVC_RPS_ST_CURR_AFTER : 0),
914 vpic->reference_frames[
i] = (VAPictureHEVC) {
915 .picture_id = VA_INVALID_ID,
916 .flags = VA_PICTURE_HEVC_INVALID,
926 vpic->pic_fields.bits.idr_pic_flag = 1;
927 vpic->pic_fields.bits.coding_type = 1;
928 vpic->pic_fields.bits.reference_pic_flag = 1;
931 vpic->pic_fields.bits.idr_pic_flag = 0;
932 vpic->pic_fields.bits.coding_type = 1;
933 vpic->pic_fields.bits.reference_pic_flag = 1;
936 vpic->pic_fields.bits.idr_pic_flag = 0;
937 vpic->pic_fields.bits.coding_type = 2;
938 vpic->pic_fields.bits.reference_pic_flag = 1;
941 vpic->pic_fields.bits.idr_pic_flag = 0;
942 vpic->pic_fields.bits.coding_type = 3;
943 vpic->pic_fields.bits.reference_pic_flag = 0;
969 .nuh_temporal_id_plus1 = 1,
983 (1 << (
sps->log2_max_pic_order_cnt_lsb_minus4 + 4)) - 1;
990 int i, j, poc, rps_pics;
995 memset(rps, 0,
sizeof(*rps));
1001 rps_used[rps_pics] = 1;
1005 if (pic->
dpb[
i] == pic)
1007 for (j = 0; j < pic->
nb_refs; j++) {
1011 if (j < pic->nb_refs)
1015 rps_used[rps_pics] = 0;
1019 for (
i = 1;
i < rps_pics;
i++) {
1020 for (j =
i; j > 0; j--) {
1021 if (rps_poc[j] > rps_poc[j - 1])
1024 FFSWAP(
int, rps_poc[j], rps_poc[j - 1]);
1025 FFSWAP(
int, rps_used[j], rps_used[j - 1]);
1031 for (
i = 0;
i < rps_pics;
i++) {
1033 rps_poc[
i], rps_used[
i]);
1037 for (
i = 0;
i < rps_pics;
i++) {
1045 for (j =
i - 1; j >= 0; j--) {
1053 for (j =
i; j < rps_pics; j++) {
1065 sps->sps_temporal_mvp_enabled_flag;
1078 sps->sample_adaptive_offset_enabled_flag;
1088 *vslice = (VAEncSliceParameterBufferHEVC) {
1110 .slice_fields.bits = {
1114 .slice_temporal_mvp_enabled_flag =
1118 .num_ref_idx_active_override_flag =
1122 .slice_deblocking_filter_disabled_flag =
1124 .slice_loop_filter_across_slices_enabled_flag =
1131 vslice->ref_pic_list0[
i].picture_id = VA_INVALID_ID;
1132 vslice->ref_pic_list0[
i].flags = VA_PICTURE_HEVC_INVALID;
1133 vslice->ref_pic_list1[
i].picture_id = VA_INVALID_ID;
1134 vslice->ref_pic_list1[
i].flags = VA_PICTURE_HEVC_INVALID;
1142 vslice->ref_pic_list0[0] = vpic->reference_frames[0];
1145 vslice->ref_pic_list1[0] = vpic->reference_frames[0];
1150 vslice->ref_pic_list1[0] = vpic->reference_frames[1];
1156 vslice->ref_pic_list1[
i].picture_id = vslice->ref_pic_list0[
i].picture_id;
1157 vslice->ref_pic_list1[
i].flags = vslice->ref_pic_list0[
i].flags;
1169 #if VA_CHECK_VERSION(1, 13, 0)
1171 VAConfigAttribValEncHEVCBlockSizes block_size;
1172 VAConfigAttrib attr;
1175 attr.type = VAConfigAttribEncHEVCFeatures;
1176 vas = vaGetConfigAttributes(
ctx->hwctx->display,
ctx->va_profile,
1177 ctx->va_entrypoint, &attr, 1);
1178 if (vas != VA_STATUS_SUCCESS) {
1180 "features, using guessed defaults.\n");
1182 }
else if (attr.value == VA_ATTRIB_NOT_SUPPORTED) {
1184 "encoder features, using guessed defaults.\n");
1189 attr.type = VAConfigAttribEncHEVCBlockSizes;
1190 vas = vaGetConfigAttributes(
ctx->hwctx->display,
ctx->va_profile,
1191 ctx->va_entrypoint, &attr, 1);
1192 if (vas != VA_STATUS_SUCCESS) {
1194 "block size, using guessed defaults.\n");
1196 }
else if (attr.value == VA_ATTRIB_NOT_SUPPORTED) {
1198 "encoder block size, using guessed defaults.\n");
1200 priv->
va_bs = block_size.value = attr.value;
1203 1 << block_size.bits.log2_max_coding_tree_block_size_minus3 + 3;
1205 1 << block_size.bits.log2_min_luma_coding_block_size_minus3 + 3;
1221 ctx->slice_block_width =
ctx->slice_block_height = priv->
ctu_size;
1236 if (
ctx->va_rc_mode == VA_RC_CQP) {
1256 "%d / %d / %d for IDR- / P- / B-frames.\n",
1266 ctx->roi_quant_range = 51 + 6 * (
ctx->profile->depth - 8);
1274 #if VA_CHECK_VERSION(0, 37, 0)
1278 #if VA_CHECK_VERSION(1, 2, 0)
1293 .default_quality = 25,
1300 .sequence_params_size =
sizeof(VAEncSequenceParameterBufferHEVC),
1303 .picture_params_size =
sizeof(VAEncPictureParameterBufferHEVC),
1306 .slice_params_size =
sizeof(VAEncSliceParameterBufferHEVC),
1309 .sequence_header_type = VAEncPackedHeaderSequence,
1312 .slice_header_type = VAEncPackedHeaderHEVC_Slice,
1332 "in 8-bit unsigned integer.\n", avctx->
level);
1336 ctx->desired_packed_headers =
1337 VA_ENC_PACKED_HEADER_SEQUENCE |
1338 VA_ENC_PACKED_HEADER_SLICE |
1339 VA_ENC_PACKED_HEADER_MISC;
1342 ctx->explicit_qp = priv->
qp;
1357 #define OFFSET(x) offsetof(VAAPIEncodeH265Context, x)
1358 #define FLAGS (AV_OPT_FLAG_VIDEO_PARAM | AV_OPT_FLAG_ENCODING_PARAM)
1363 {
"qp",
"Constant QP (for P-frames; scaled by qfactor/qoffset for I/B)",
1366 {
"aud",
"Include AUD",
1369 {
"profile",
"Set profile (general_profile_idc)",
1373 #define PROFILE(name, value) name, NULL, 0, AV_OPT_TYPE_CONST, \
1374 { .i64 = value }, 0, 0, FLAGS, "profile"
1380 {
"tier",
"Set tier (general_tier_flag)",
1382 { .i64 = 0 }, 0, 1,
FLAGS,
"tier" },
1384 { .i64 = 0 }, 0, 0,
FLAGS,
"tier" },
1386 { .i64 = 1 }, 0, 0,
FLAGS,
"tier" },
1388 {
"level",
"Set level (general_level_idc)",
1392 #define LEVEL(name, value) name, NULL, 0, AV_OPT_TYPE_CONST, \
1393 { .i64 = value }, 0, 0, FLAGS, "level"
1396 {
LEVEL(
"2.1", 63) },
1398 {
LEVEL(
"3.1", 93) },
1399 {
LEVEL(
"4", 120) },
1400 {
LEVEL(
"4.1", 123) },
1401 {
LEVEL(
"5", 150) },
1402 {
LEVEL(
"5.1", 153) },
1403 {
LEVEL(
"5.2", 156) },
1404 {
LEVEL(
"6", 180) },
1405 {
LEVEL(
"6.1", 183) },
1406 {
LEVEL(
"6.2", 186) },
1409 {
"sei",
"Set SEI to include",
1412 0, INT_MAX,
FLAGS,
"sei" },
1414 "Include HDR metadata for mastering display colour volume "
1415 "and content light level information",
1418 INT_MIN, INT_MAX,
FLAGS,
"sei" },
1420 {
"tiles",
"Tile columns x rows",
1431 {
"i_qfactor",
"1" },
1432 {
"i_qoffset",
"0" },
1433 {
"b_qfactor",
"6/5" },
1434 {
"b_qoffset",
"0" },
1448 .
p.
name =
"hevc_vaapi",
1466 .p.wrapper_name =
"vaapi",