22 #include <va/va_enc_hevc.h>
101 char *
data,
size_t *data_len,
115 "%zu < %zu.\n", *data_len,
137 "type = %d.\n",
header->nal_unit_type);
145 char *
data,
size_t *data_len)
179 char *
data,
size_t *data_len)
205 char *
data,
size_t *data_len)
250 *
type = VAEncPackedHeaderRawData;
270 VAEncSequenceParameterBufferHEVC *vseq =
ctx->codec_sequence_params;
271 VAEncPictureParameterBufferHEVC *vpic =
ctx->codec_picture_params;
276 memset(
vps, 0,
sizeof(*
vps));
277 memset(
sps, 0,
sizeof(*
sps));
278 memset(
pps, 0,
sizeof(*
pps));
283 if (
desc->nb_components == 1) {
286 if (
desc->log2_chroma_w == 1 &&
desc->log2_chroma_h == 1) {
288 }
else if (
desc->log2_chroma_w == 1 &&
desc->log2_chroma_h == 0) {
290 }
else if (
desc->log2_chroma_w == 0 &&
desc->log2_chroma_h == 0) {
294 "%s is not supported.\n",
desc->name);
306 .nuh_temporal_id_plus1 = 1,
309 vps->vps_video_parameter_set_id = 0;
311 vps->vps_base_layer_internal_flag = 1;
312 vps->vps_base_layer_available_flag = 1;
313 vps->vps_max_layers_minus1 = 0;
314 vps->vps_max_sub_layers_minus1 = 0;
315 vps->vps_temporal_id_nesting_flag = 1;
355 ctx->surface_width,
ctx->surface_height,
356 ctx->nb_slices,
ctx->tile_rows,
ctx->tile_cols,
357 (
ctx->b_per_p > 0) + 1);
363 "any normal level; using level 8.5.\n");
370 vps->vps_sub_layer_ordering_info_present_flag = 0;
371 vps->vps_max_dec_pic_buffering_minus1[0] =
ctx->max_b_depth + 1;
372 vps->vps_max_num_reorder_pics[0] =
ctx->max_b_depth;
373 vps->vps_max_latency_increase_plus1[0] = 0;
375 vps->vps_max_layer_id = 0;
376 vps->vps_num_layer_sets_minus1 = 0;
377 vps->layer_id_included_flag[0][0] = 1;
379 vps->vps_timing_info_present_flag = 1;
383 vps->vps_poc_proportional_to_timing_flag = 1;
384 vps->vps_num_ticks_poc_diff_one_minus1 = 0;
388 vps->vps_poc_proportional_to_timing_flag = 0;
390 vps->vps_num_hrd_parameters = 0;
398 .nuh_temporal_id_plus1 = 1,
401 sps->sps_video_parameter_set_id =
vps->vps_video_parameter_set_id;
403 sps->sps_max_sub_layers_minus1 =
vps->vps_max_sub_layers_minus1;
404 sps->sps_temporal_id_nesting_flag =
vps->vps_temporal_id_nesting_flag;
406 sps->profile_tier_level =
vps->profile_tier_level;
408 sps->sps_seq_parameter_set_id = 0;
410 sps->chroma_format_idc = chroma_format;
411 sps->separate_colour_plane_flag = 0;
413 sps->pic_width_in_luma_samples =
ctx->surface_width;
414 sps->pic_height_in_luma_samples =
ctx->surface_height;
416 if (avctx->
width !=
ctx->surface_width ||
418 sps->conformance_window_flag = 1;
419 sps->conf_win_left_offset = 0;
420 sps->conf_win_right_offset =
421 (
ctx->surface_width - avctx->
width) >>
desc->log2_chroma_w;
422 sps->conf_win_top_offset = 0;
423 sps->conf_win_bottom_offset =
424 (
ctx->surface_height - avctx->
height) >>
desc->log2_chroma_h;
426 sps->conformance_window_flag = 0;
432 sps->log2_max_pic_order_cnt_lsb_minus4 = 8;
434 sps->sps_sub_layer_ordering_info_present_flag =
435 vps->vps_sub_layer_ordering_info_present_flag;
436 for (
i = 0;
i <=
sps->sps_max_sub_layers_minus1;
i++) {
437 sps->sps_max_dec_pic_buffering_minus1[
i] =
438 vps->vps_max_dec_pic_buffering_minus1[
i];
439 sps->sps_max_num_reorder_pics[
i] =
440 vps->vps_max_num_reorder_pics[
i];
441 sps->sps_max_latency_increase_plus1[
i] =
442 vps->vps_max_latency_increase_plus1[
i];
449 sps->log2_min_luma_coding_block_size_minus3 = 0;
450 sps->log2_diff_max_min_luma_coding_block_size = 2;
452 sps->log2_min_luma_transform_block_size_minus2 = 0;
453 sps->log2_diff_max_min_luma_transform_block_size = 3;
455 sps->max_transform_hierarchy_depth_inter = 3;
456 sps->max_transform_hierarchy_depth_intra = 3;
458 sps->amp_enabled_flag = 1;
460 sps->sample_adaptive_offset_enabled_flag = 0;
461 sps->sps_temporal_mvp_enabled_flag = 0;
463 sps->pcm_enabled_flag = 0;
466 #if VA_CHECK_VERSION(1, 13, 0)
468 VAConfigAttribValEncHEVCFeatures features = { .value = priv->
va_features };
471 sps->amp_enabled_flag =
473 sps->sample_adaptive_offset_enabled_flag =
475 sps->sps_temporal_mvp_enabled_flag =
476 !!features.bits.temporal_mvp;
477 sps->pcm_enabled_flag =
482 VAConfigAttribValEncHEVCBlockSizes bs = { .value = priv->
va_bs };
483 sps->log2_min_luma_coding_block_size_minus3 =
485 sps->log2_diff_max_min_luma_coding_block_size =
488 sps->log2_min_luma_transform_block_size_minus2 =
489 bs.bits.log2_min_luma_transform_block_size_minus2;
490 sps->log2_diff_max_min_luma_transform_block_size =
491 bs.bits.log2_max_luma_transform_block_size_minus2 -
492 bs.bits.log2_min_luma_transform_block_size_minus2;
494 sps->max_transform_hierarchy_depth_inter =
495 bs.bits.max_max_transform_hierarchy_depth_inter;
496 sps->max_transform_hierarchy_depth_intra =
497 bs.bits.max_max_transform_hierarchy_depth_intra;
504 sps->num_short_term_ref_pic_sets = 0;
505 sps->long_term_ref_pics_present_flag = 0;
507 sps->vui_parameters_present_flag = 1;
572 .nuh_temporal_id_plus1 = 1,
575 pps->pps_pic_parameter_set_id = 0;
576 pps->pps_seq_parameter_set_id =
sps->sps_seq_parameter_set_id;
578 pps->num_ref_idx_l0_default_active_minus1 = 0;
579 pps->num_ref_idx_l1_default_active_minus1 = 0;
583 pps->cu_qp_delta_enabled_flag = (
ctx->va_rc_mode != VA_RC_CQP);
584 pps->diff_cu_qp_delta_depth = 0;
587 #if VA_CHECK_VERSION(1, 13, 0)
589 VAConfigAttribValEncHEVCFeatures features = { .value = priv->
va_features };
590 if (
ctx->va_rc_mode != VA_RC_CQP)
591 pps->cu_qp_delta_enabled_flag =
592 !!features.bits.cu_qp_delta;
594 pps->transform_skip_enabled_flag =
595 !!features.bits.transform_skip;
598 if (
pps->cu_qp_delta_enabled_flag)
599 pps->diff_cu_qp_delta_depth =
sps->log2_diff_max_min_luma_coding_block_size;
603 if (
ctx->tile_rows &&
ctx->tile_cols) {
606 pps->tiles_enabled_flag = 1;
607 pps->num_tile_columns_minus1 =
ctx->tile_cols - 1;
608 pps->num_tile_rows_minus1 =
ctx->tile_rows - 1;
613 for (
i = 0;
i <=
pps->num_tile_columns_minus1 &&
614 uniform_spacing;
i++) {
615 if (
ctx->col_width[
i] !=
616 (
i + 1) *
ctx->slice_block_cols /
ctx->tile_cols -
617 i *
ctx->slice_block_cols /
ctx->tile_cols)
620 for (
i = 0;
i <=
pps->num_tile_rows_minus1 &&
621 uniform_spacing;
i++) {
622 if (
ctx->row_height[
i] !=
623 (
i + 1) *
ctx->slice_block_rows /
ctx->tile_rows -
624 i *
ctx->slice_block_rows /
ctx->tile_rows)
627 pps->uniform_spacing_flag = uniform_spacing;
629 for (
i = 0;
i <=
pps->num_tile_columns_minus1;
i++)
630 pps->column_width_minus1[
i] =
ctx->col_width[
i] - 1;
631 for (
i = 0;
i <=
pps->num_tile_rows_minus1;
i++)
632 pps->row_height_minus1[
i] =
ctx->row_height[
i] - 1;
634 pps->loop_filter_across_tiles_enabled_flag = 1;
637 pps->pps_loop_filter_across_slices_enabled_flag = 1;
641 *vseq = (VAEncSequenceParameterBufferHEVC) {
642 .general_profile_idc =
vps->profile_tier_level.general_profile_idc,
643 .general_level_idc =
vps->profile_tier_level.general_level_idc,
644 .general_tier_flag =
vps->profile_tier_level.general_tier_flag,
646 .intra_period =
ctx->gop_size,
647 .intra_idr_period =
ctx->gop_size,
648 .ip_period =
ctx->b_per_p + 1,
649 .bits_per_second =
ctx->va_bit_rate,
651 .pic_width_in_luma_samples =
sps->pic_width_in_luma_samples,
652 .pic_height_in_luma_samples =
sps->pic_height_in_luma_samples,
655 .chroma_format_idc =
sps->chroma_format_idc,
656 .separate_colour_plane_flag =
sps->separate_colour_plane_flag,
657 .bit_depth_luma_minus8 =
sps->bit_depth_luma_minus8,
658 .bit_depth_chroma_minus8 =
sps->bit_depth_chroma_minus8,
659 .scaling_list_enabled_flag =
sps->scaling_list_enabled_flag,
660 .strong_intra_smoothing_enabled_flag =
661 sps->strong_intra_smoothing_enabled_flag,
662 .amp_enabled_flag =
sps->amp_enabled_flag,
663 .sample_adaptive_offset_enabled_flag =
664 sps->sample_adaptive_offset_enabled_flag,
665 .pcm_enabled_flag =
sps->pcm_enabled_flag,
666 .pcm_loop_filter_disabled_flag =
sps->pcm_loop_filter_disabled_flag,
667 .sps_temporal_mvp_enabled_flag =
sps->sps_temporal_mvp_enabled_flag,
670 .log2_min_luma_coding_block_size_minus3 =
671 sps->log2_min_luma_coding_block_size_minus3,
672 .log2_diff_max_min_luma_coding_block_size =
673 sps->log2_diff_max_min_luma_coding_block_size,
674 .log2_min_transform_block_size_minus2 =
675 sps->log2_min_luma_transform_block_size_minus2,
676 .log2_diff_max_min_transform_block_size =
677 sps->log2_diff_max_min_luma_transform_block_size,
678 .max_transform_hierarchy_depth_inter =
679 sps->max_transform_hierarchy_depth_inter,
680 .max_transform_hierarchy_depth_intra =
681 sps->max_transform_hierarchy_depth_intra,
683 .pcm_sample_bit_depth_luma_minus1 =
684 sps->pcm_sample_bit_depth_luma_minus1,
685 .pcm_sample_bit_depth_chroma_minus1 =
686 sps->pcm_sample_bit_depth_chroma_minus1,
687 .log2_min_pcm_luma_coding_block_size_minus3 =
688 sps->log2_min_pcm_luma_coding_block_size_minus3,
689 .log2_max_pcm_luma_coding_block_size_minus3 =
690 sps->log2_min_pcm_luma_coding_block_size_minus3 +
691 sps->log2_diff_max_min_pcm_luma_coding_block_size,
693 .vui_parameters_present_flag = 0,
696 *vpic = (VAEncPictureParameterBufferHEVC) {
697 .decoded_curr_pic = {
698 .picture_id = VA_INVALID_ID,
699 .flags = VA_PICTURE_HEVC_INVALID,
702 .coded_buf = VA_INVALID_ID,
704 .collocated_ref_pic_index =
sps->sps_temporal_mvp_enabled_flag ?
708 .pic_init_qp =
pps->init_qp_minus26 + 26,
709 .diff_cu_qp_delta_depth =
pps->diff_cu_qp_delta_depth,
710 .pps_cb_qp_offset =
pps->pps_cb_qp_offset,
711 .pps_cr_qp_offset =
pps->pps_cr_qp_offset,
713 .num_tile_columns_minus1 =
pps->num_tile_columns_minus1,
714 .num_tile_rows_minus1 =
pps->num_tile_rows_minus1,
716 .log2_parallel_merge_level_minus2 =
pps->log2_parallel_merge_level_minus2,
717 .ctu_max_bitsize_allowed = 0,
719 .num_ref_idx_l0_default_active_minus1 =
720 pps->num_ref_idx_l0_default_active_minus1,
721 .num_ref_idx_l1_default_active_minus1 =
722 pps->num_ref_idx_l1_default_active_minus1,
724 .slice_pic_parameter_set_id =
pps->pps_pic_parameter_set_id,
727 .sign_data_hiding_enabled_flag =
pps->sign_data_hiding_enabled_flag,
728 .constrained_intra_pred_flag =
pps->constrained_intra_pred_flag,
729 .transform_skip_enabled_flag =
pps->transform_skip_enabled_flag,
730 .cu_qp_delta_enabled_flag =
pps->cu_qp_delta_enabled_flag,
731 .weighted_pred_flag =
pps->weighted_pred_flag,
732 .weighted_bipred_flag =
pps->weighted_bipred_flag,
733 .transquant_bypass_enabled_flag =
pps->transquant_bypass_enabled_flag,
734 .tiles_enabled_flag =
pps->tiles_enabled_flag,
735 .entropy_coding_sync_enabled_flag =
pps->entropy_coding_sync_enabled_flag,
736 .loop_filter_across_tiles_enabled_flag =
737 pps->loop_filter_across_tiles_enabled_flag,
738 .pps_loop_filter_across_slices_enabled_flag =
739 pps->pps_loop_filter_across_slices_enabled_flag,
740 .scaling_list_data_present_flag = (
sps->sps_scaling_list_data_present_flag |
741 pps->pps_scaling_list_data_present_flag),
742 .screen_content_flag = 0,
743 .enable_gpu_weighted_prediction = 0,
744 .no_output_of_prior_pics_flag = 0,
748 if (
pps->tiles_enabled_flag) {
749 for (
i = 0;
i <= vpic->num_tile_rows_minus1;
i++)
750 vpic->row_height_minus1[
i] =
pps->row_height_minus1[
i];
751 for (
i = 0;
i <= vpic->num_tile_columns_minus1;
i++)
752 vpic->column_width_minus1[
i] =
pps->column_width_minus1[
i];
793 for (irap_ref = pic; irap_ref; irap_ref = irap_ref->
refs[1][0]) {
816 .nuh_temporal_id_plus1 = 1,
843 const int mapping[3] = {1, 2, 0};
844 const int chroma_den = 50000;
845 const int luma_den = 10000;
847 for (
i = 0;
i < 3;
i++) {
848 const int j = mapping[
i];
890 clli->max_pic_average_light_level =
FFMIN(clm->
MaxFALL, 65535);
898 size_t sei_a53cc_len;
912 vpic->decoded_curr_pic = (VAPictureHEVC) {
924 href =
ref->priv_data;
926 vpic->reference_frames[j++] = (VAPictureHEVC) {
927 .picture_id =
ref->recon_surface,
930 VA_PICTURE_HEVC_RPS_ST_CURR_BEFORE : 0) |
932 VA_PICTURE_HEVC_RPS_ST_CURR_AFTER : 0),
938 vpic->reference_frames[j] = (VAPictureHEVC) {
939 .picture_id = VA_INVALID_ID,
940 .flags = VA_PICTURE_HEVC_INVALID,
950 vpic->pic_fields.bits.idr_pic_flag = 1;
951 vpic->pic_fields.bits.coding_type = 1;
952 vpic->pic_fields.bits.reference_pic_flag = 1;
955 vpic->pic_fields.bits.idr_pic_flag = 0;
956 vpic->pic_fields.bits.coding_type = 1;
957 vpic->pic_fields.bits.reference_pic_flag = 1;
960 vpic->pic_fields.bits.idr_pic_flag = 0;
961 vpic->pic_fields.bits.coding_type = 2;
962 vpic->pic_fields.bits.reference_pic_flag = 1;
965 vpic->pic_fields.bits.idr_pic_flag = 0;
966 vpic->pic_fields.bits.coding_type = 3;
967 vpic->pic_fields.bits.reference_pic_flag = 0;
993 .nuh_temporal_id_plus1 = 1,
1007 (1 << (
sps->log2_max_pic_order_cnt_lsb_minus4 + 4)) - 1;
1014 int i, j, poc, rps_pics;
1019 memset(rps, 0,
sizeof(*rps));
1023 for (j = 0; j < pic->
nb_refs[
i]; j++) {
1026 rps_used[rps_pics] = 1;
1032 if (pic->
dpb[
i] == pic)
1035 for (j = 0; j < pic->
nb_refs[0]; j++) {
1036 if (pic->
dpb[
i] == pic->
refs[0][j])
1039 if (j < pic->nb_refs[0])
1042 for (j = 0; j < pic->
nb_refs[1]; j++) {
1043 if (pic->
dpb[
i] == pic->
refs[1][j])
1046 if (j < pic->nb_refs[1])
1051 rps_used[rps_pics] = 0;
1055 for (
i = 1;
i < rps_pics;
i++) {
1056 for (j =
i; j > 0; j--) {
1057 if (rps_poc[j] > rps_poc[j - 1])
1060 FFSWAP(
int, rps_poc[j], rps_poc[j - 1]);
1061 FFSWAP(
int, rps_used[j], rps_used[j - 1]);
1067 for (
i = 0;
i < rps_pics;
i++) {
1069 rps_poc[
i], rps_used[
i]);
1073 for (
i = 0;
i < rps_pics;
i++) {
1081 for (j =
i - 1; j >= 0; j--) {
1089 for (j =
i; j < rps_pics; j++) {
1101 sps->sps_temporal_mvp_enabled_flag;
1114 sps->sample_adaptive_offset_enabled_flag;
1124 *vslice = (VAEncSliceParameterBufferHEVC) {
1146 .slice_fields.bits = {
1150 .slice_temporal_mvp_enabled_flag =
1154 .num_ref_idx_active_override_flag =
1158 .slice_deblocking_filter_disabled_flag =
1160 .slice_loop_filter_across_slices_enabled_flag =
1167 vslice->ref_pic_list0[
i].picture_id = VA_INVALID_ID;
1168 vslice->ref_pic_list0[
i].flags = VA_PICTURE_HEVC_INVALID;
1169 vslice->ref_pic_list1[
i].picture_id = VA_INVALID_ID;
1170 vslice->ref_pic_list1[
i].flags = VA_PICTURE_HEVC_INVALID;
1177 vslice->ref_pic_list0[0] = vpic->reference_frames[0];
1180 vslice->ref_pic_list1[0] = vpic->reference_frames[0];
1185 vslice->ref_pic_list1[0] = vpic->reference_frames[1];
1191 vslice->ref_pic_list1[
i].picture_id = vslice->ref_pic_list0[
i].picture_id;
1192 vslice->ref_pic_list1[
i].flags = vslice->ref_pic_list0[
i].flags;
1204 #if VA_CHECK_VERSION(1, 13, 0)
1206 VAConfigAttribValEncHEVCBlockSizes block_size;
1207 VAConfigAttrib attr;
1210 attr.type = VAConfigAttribEncHEVCFeatures;
1211 vas = vaGetConfigAttributes(
ctx->hwctx->display,
ctx->va_profile,
1212 ctx->va_entrypoint, &attr, 1);
1213 if (vas != VA_STATUS_SUCCESS) {
1215 "features, using guessed defaults.\n");
1217 }
else if (attr.value == VA_ATTRIB_NOT_SUPPORTED) {
1219 "encoder features, using guessed defaults.\n");
1224 attr.type = VAConfigAttribEncHEVCBlockSizes;
1225 vas = vaGetConfigAttributes(
ctx->hwctx->display,
ctx->va_profile,
1226 ctx->va_entrypoint, &attr, 1);
1227 if (vas != VA_STATUS_SUCCESS) {
1229 "block size, using guessed defaults.\n");
1231 }
else if (attr.value == VA_ATTRIB_NOT_SUPPORTED) {
1233 "encoder block size, using guessed defaults.\n");
1235 priv->
va_bs = block_size.value = attr.value;
1238 1 << block_size.bits.log2_max_coding_tree_block_size_minus3 + 3;
1240 1 << block_size.bits.log2_min_luma_coding_block_size_minus3 + 3;
1256 ctx->slice_block_width =
ctx->slice_block_height = priv->
ctu_size;
1271 if (
ctx->va_rc_mode == VA_RC_CQP) {
1291 "%d / %d / %d for IDR- / P- / B-frames.\n",
1301 ctx->roi_quant_range = 51 + 6 * (
ctx->profile->depth - 8);
1309 #if VA_CHECK_VERSION(0, 37, 0)
1313 #if VA_CHECK_VERSION(1, 2, 0)
1333 .default_quality = 25,
1340 .sequence_params_size =
sizeof(VAEncSequenceParameterBufferHEVC),
1343 .picture_params_size =
sizeof(VAEncPictureParameterBufferHEVC),
1346 .slice_params_size =
sizeof(VAEncSliceParameterBufferHEVC),
1349 .sequence_header_type = VAEncPackedHeaderSequence,
1352 .slice_header_type = VAEncPackedHeaderHEVC_Slice,
1372 "in 8-bit unsigned integer.\n", avctx->
level);
1376 ctx->desired_packed_headers =
1377 VA_ENC_PACKED_HEADER_SEQUENCE |
1378 VA_ENC_PACKED_HEADER_SLICE |
1379 VA_ENC_PACKED_HEADER_MISC;
1382 ctx->explicit_qp = priv->
qp;
1398 #define OFFSET(x) offsetof(VAAPIEncodeH265Context, x)
1399 #define FLAGS (AV_OPT_FLAG_VIDEO_PARAM | AV_OPT_FLAG_ENCODING_PARAM)
1404 {
"qp",
"Constant QP (for P-frames; scaled by qfactor/qoffset for I/B)",
1407 {
"aud",
"Include AUD",
1410 {
"profile",
"Set profile (general_profile_idc)",
1414 #define PROFILE(name, value) name, NULL, 0, AV_OPT_TYPE_CONST, \
1415 { .i64 = value }, 0, 0, FLAGS, "profile"
1421 {
"tier",
"Set tier (general_tier_flag)",
1423 { .i64 = 0 }, 0, 1,
FLAGS,
"tier" },
1425 { .i64 = 0 }, 0, 0,
FLAGS,
"tier" },
1427 { .i64 = 1 }, 0, 0,
FLAGS,
"tier" },
1429 {
"level",
"Set level (general_level_idc)",
1433 #define LEVEL(name, value) name, NULL, 0, AV_OPT_TYPE_CONST, \
1434 { .i64 = value }, 0, 0, FLAGS, "level"
1437 {
LEVEL(
"2.1", 63) },
1439 {
LEVEL(
"3.1", 93) },
1440 {
LEVEL(
"4", 120) },
1441 {
LEVEL(
"4.1", 123) },
1442 {
LEVEL(
"5", 150) },
1443 {
LEVEL(
"5.1", 153) },
1444 {
LEVEL(
"5.2", 156) },
1445 {
LEVEL(
"6", 180) },
1446 {
LEVEL(
"6.1", 183) },
1447 {
LEVEL(
"6.2", 186) },
1450 {
"sei",
"Set SEI to include",
1453 0, INT_MAX,
FLAGS,
"sei" },
1455 "Include HDR metadata for mastering display colour volume "
1456 "and content light level information",
1459 INT_MIN, INT_MAX,
FLAGS,
"sei" },
1461 "Include A/53 caption data",
1464 INT_MIN, INT_MAX,
FLAGS,
"sei" },
1466 {
"tiles",
"Tile columns x rows",
1477 {
"i_qfactor",
"1" },
1478 {
"i_qoffset",
"0" },
1479 {
"b_qfactor",
"6/5" },
1480 {
"b_qoffset",
"0" },
1494 .
p.
name =
"hevc_vaapi",
1513 .p.wrapper_name =
"vaapi",