23 #if HAVE_GETAUXVAL || HAVE_ELF_AUX_INFO
27 #define HWCAP_AARCH64_PMULL (1 << 4)
28 #define HWCAP_AARCH64_CRC32 (1 << 7)
29 #define HWCAP_AARCH64_SHA3 (1 << 17)
30 #define HWCAP_AARCH64_ASIMDDP (1 << 20)
31 #define HWCAP_AARCH64_SVE (1 << 22)
32 #define HWCAP2_AARCH64_SVE2 (1 << 1)
33 #define HWCAP2_AARCH64_I8MM (1 << 13)
34 #define HWCAP2_AARCH64_SME (1 << 23)
35 #define HWCAP2_AARCH64_SME_I16I64 (1 << 24)
36 #define HWCAP2_AARCH64_SME2 (1ULL << 37)
45 if (hwcap & HWCAP_AARCH64_PMULL)
47 if (hwcap & HWCAP_AARCH64_SHA3)
49 if (hwcap & HWCAP_AARCH64_CRC32)
51 if (hwcap & HWCAP_AARCH64_ASIMDDP)
53 if (hwcap & HWCAP_AARCH64_SVE)
55 if (hwcap2 & HWCAP2_AARCH64_SVE2)
57 if (hwcap2 & HWCAP2_AARCH64_I8MM)
59 if (hwcap2 & HWCAP2_AARCH64_SME)
61 if (hwcap2 & HWCAP2_AARCH64_SME_I16I64)
63 if (hwcap2 & HWCAP2_AARCH64_SME2)
69 #elif defined(__APPLE__) && HAVE_SYSCTLBYNAME
70 #include <sys/sysctl.h>
72 static int have_feature(
const char *feature) {
84 if (have_feature(
"hw.optional.arm.FEAT_DotProd"))
86 if (have_feature(
"hw.optional.arm.FEAT_I8MM"))
88 if (have_feature(
"hw.optional.arm.FEAT_SME"))
90 if (have_feature(
"hw.optional.arm.FEAT_SME_I16I64"))
92 if (have_feature(
"hw.optional.armv8_crc32"))
94 if (have_feature(
"hw.optional.arm.FEAT_PMULL"))
96 if (have_feature(
"hw.optional.armv8_2_sha3"))
98 if (have_feature(
"hw.optional.arm.FEAT_SME2"))
104 #elif defined(__OpenBSD__)
105 #include <machine/armreg.h>
106 #include <machine/cpu.h>
107 #include <sys/types.h>
108 #include <sys/sysctl.h>
114 #ifdef CPU_ID_AA64ISAR0
120 mib[0] = CTL_MACHDEP;
121 mib[1] = CPU_ID_AA64ISAR0;
123 if (sysctl(mib, 2, &isar0, &
len,
NULL, 0) != -1) {
124 if (ID_AA64ISAR0_DP(isar0) >= ID_AA64ISAR0_DP_IMPL)
126 if (ID_AA64ISAR0_CRC32(isar0) >= ID_AA64ISAR0_CRC32_BASE)
128 if (ID_AA64ISAR0_AES(isar0) >= ID_AA64ISAR0_AES_PMULL)
130 if (ID_AA64ISAR0_SHA3(isar0) >= ID_AA64ISAR0_SHA3_IMPL)
134 mib[0] = CTL_MACHDEP;
135 mib[1] = CPU_ID_AA64ISAR1;
137 if (sysctl(mib, 2, &isar1, &
len,
NULL, 0) != -1) {
138 #ifdef ID_AA64ISAR1_I8MM_IMPL
139 if (ID_AA64ISAR1_I8MM(isar1) >= ID_AA64ISAR1_I8MM_IMPL)
148 #elif defined(_WIN32)
154 #ifdef PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE
155 if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE))
158 #ifdef PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE
159 if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE))
162 #ifdef PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE
163 if (IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE))
166 #ifdef PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE
167 if (IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE))
170 #ifdef PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE
171 if (IsProcessorFeaturePresent(PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE))
174 #ifdef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE
175 if (IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE))
178 #ifdef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
179 if (IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE))
182 #ifdef PF_ARM_SME_INSTRUCTIONS_AVAILABLE
183 if (IsProcessorFeaturePresent(PF_ARM_SME_INSTRUCTIONS_AVAILABLE))
186 #ifdef PF_ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE
187 if (IsProcessorFeaturePresent(PF_ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE))
190 #ifdef PF_ARM_SME2_INSTRUCTIONS_AVAILABLE
191 if (IsProcessorFeaturePresent(PF_ARM_SME2_INSTRUCTIONS_AVAILABLE))
210 #ifdef __ARM_FEATURE_DOTPROD
213 #ifdef __ARM_FEATURE_MATMUL_INT8
216 #ifdef __ARM_FEATURE_SVE
219 #ifdef __ARM_FEATURE_SVE2
222 #ifdef __ARM_FEATURE_SME
225 #ifdef __ARM_FEATURE_CRC32
228 #ifdef __ARM_FEATURE_AES
231 #ifdef __ARM_FEATURE_SHA3
234 #ifdef __ARM_FEATURE_SME_I16I64
237 #ifdef __ARM_FEATURE_SME2